1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a data input/output line structure having reduced resistance.
2. Description of the Related Art
In general, one way of improving performance of a computer system is to improve performance of the memory associated with the central processing unit (CPU) in addition to improving the operating speed of the CPU itself. The performance of the memory device can be improved by increasing its bandwidth per unit time. The amount of data that can be read from or written to a memory at any one time is a function of the number of data input/output lines available from the memory. Thus, depending on the number of data input/output lines, bit line data of memory cells are selectively transferred to the data input/output lines through data input/output circuits.
As semiconductor memory capacity increases, chip sizes and lengths of internal lines are also increased. The lengthened data lines, such as word lines, bit lines and data input/output lines, degrade speed and power performance of the semiconductor memory device. A word line strapping method can be used to reduce the effects from long lines. For example, a metallic line can be formed on a gate polysilicon to reduce delay in word lines.
Data input/output lines are often the final paths of travel for data of memory cells. Data read/write speed of a semiconductor memory device is affected by line load on the data input/output lines. That is, the operation speed of the semiconductor memory device is determined either by a time period from when data to be read from the memory cell is sensed to when the data is output via the data input/output lines, or by a time period required to transmit data to be written to the memory cell from the data input/output lines. Thus, increased resistance of the data input/output lines due to longer line lengths at the data input/output lines degrades the operating speed of the semiconductor memory device.
Thus, a new data input/output line structure having reduced resistance is desired to prevent a reduction in the speed of semiconductor memory devices.
It is an object of the present invention to provide a data input/output line structure having reduced resistance to improve the operation speed of semiconductor memory devices.
According to one aspect of the present invention, a semiconductor memory device includes a data input/output line structure through which data is input to or output from memory cells in a semiconductor memory device, comprising: a first signal line formed from a first metal layer, the first signal line being connected to a bit line of one of the memory cells; a second signal line formed from a second metal layer, the second signal line being parallel with the first signal line; and a plurality of strapping connectors for connecting the first signal line and the second signal line. The second metal layer may have a lower resistance than that of the first metal layer. The first and the second signal lines are arranged in parallel with each other and are also perpendicular to the bit line of the memory cell. The plurality of strapping connectors provide a plurality of connections between the first signal line and the second signal line. The connections between the first and the second signal lines are arranged at substantially regular intervals. Each of the plurality of strapping connectors also has a hole to be filled with one of the first and the second metal layers. In particular, the hole is filled with a material of one of the first and the second metal layers wherein the material filling the hole has higher penetrability than that of the other material.
In accordance with the data input/output line structure of the present invention, the resistance of the data input/output line can be reduced, thereby reducing a delay in the data input/output line.